The present invention relates generally to isolating active regions in semiconductor devices, and more particularly to shallow trench isolation (STI) processes, local oxidation of silicon (LOCOS) isolation processes, and combinations thereof.
In a typical integrated circuit, manufactured on a silicon wafer, the active devices making up the integrated circuit are divided through the use of electrically isolating material. Each of the active devices must be electrically isolated from the adjoining active region to prevent cross-over electrical effects between adjoining devices which would defeat overall operation of the circuit. Each active region is utilized by the integrated circuit manufacturer to form an active device, such as, in CMOS technology, an n-channel or a p-channel transistor. The devices are thereafter connected to a series of metal or metal-alloy interconnect structures to complete the integrated circuit device.
The processing characteristics of LOCOS regions are very well known in the art. Such regions have been in use for a long period of time and there is a great deal of knowledge in the manipulation of such processes.
There are relatively wide variations in LOCOS processes which are utilized to provide isolation between active devices in fabricating integrated circuit products. LOCOS involves growing silicon dioxide by heating an exposed area of silicon (or silicon covered with a thin layer of silicon dioxide) in an oxygen containing ambient. Prior to LOCOS growth, the wafer construct will normally be covered with an inert layer of material, such as silicon nitride (Si3N4), and the nitride layer is patterned to expose the areas selected for LOCOS formation. The localized regions of oxide are then grown in the exposed areas, and the silicon nitride layer is then removed.
Because LOCOS processes generally occupy a great deal of wafer surface area, alternative isolation structures have been developed. One such process is shallow trench isolation (STI), which involves etching a trench into the substrate, and filling the trench with an isolation material. However, shallow trench isolation is relatively complex because an anisotropic etch must be used to define the trench, the trench must be etched deeply into the silicon, and filling the trench with the isolation material can raise additional processing issues in preparing the integrated circuit.
To further complicate matters, oftentimes an integrated circuit includes several regions each having different electrical characteristics and isolation requirements. For example, a flash type electrically erasable programmable read-only-memory (EEPROM) typically includes a core array and peripheral circuit. The core array is made up of closely spaced transistors. The peripheral circuit includes both standard low voltage transistors and a high voltage peripheral section made up of high voltage transistors. Normally, the core EEPROM operational voltage range is about 10-20 volts while the operational voltage ranges of the low voltage peripheral circuit and the high voltage peripheral circuit is about 1-5 volts and about 12-26 volts, respectively. The high voltage operational voltage range is higher than the core range since the high voltage circuitry is used to generate the core voltage. These different size and voltage constraints make it desirable to provide more than one type of isolation structure between active devices within the same integrated circuit. A drawback is that the combination of such different types of isolation structures can result in an overly complex manufacturing process which is both costly and time consuming.
In view of the aforementioned shortcomings associated with conventional techniques, there is a strong need in the art for a process in which a plurality of different isolation structures may be formed on a substrate. As a particular example, there is a strong need in the art for a process whereby different isolation structures may be respectively formed for closely spaced devices, standard low voltage devices, and high voltage devices without substantial process complications. Even more particularly, there is a strong need in the art for a process for forming such different isolation structures in a flash EEPROM with minimal process complications.
According to one aspect of the invention, a method for forming isolating regions in a semiconductor substrate is provided. The method includes the steps of forming a first local oxidation of silicon (LOCOS) isolation structure on a surface of the substrate in a first region, and forming a second LOCOS isolation structure on the surface of the substrate in a second region; forming an insulating layer on the surface of the substrate and the first and second LOCOS isolation structures; forming a layer of nitride material on the insulating layer, the nitride material having a surface; patterning the nitride material and the insulating layer to provide an isolation region in the second region by exposing a portion of a surface of the second LOCOS isolation structure, and an isolation region in a third region of the substrate by exposing the surface of the substrate; removing a portion of the second LOCOS isolation structure in the isolation region in the second region to expose a portion of the surface of the substrate in the second region, such that a remaining portion of the second LOCOS isolation structure remains adjacent the isolation region in the second region; forming a trench in each of the isolation region in the second region and the isolation region in the third region, each of the trenches extending into the semiconductor substrate to a depth below the surface of the semiconductor substrate; filling the isolation region in the second region and the isolation region in the third region with an isolation oxide; removing a portion of the isolation oxide to expose the surface of the layer of nitride material, and removing the layer of nitride material such that the LOCOS isolation structure in the first region is exposed and wherein the isolation oxide fills the trench in the isolation region of the second region and the isolation region of the third region with a surface level generally even with the surface of the substrate.
According to another aspect of the invention, a method for manufacturing an integrated circuit on a semiconductor substrate is provided. The integrated circuit includes a first isolation structure including a first trench in a surface of the substrate with isolation material formed within the first trench, a second isolation structure including a first local oxidation of silicon (LOCOS) isolation structure, and a third isolation structure including a second trench in the surface of the substrate interposed between portions of a second LOCOS isolation structure. The method comprises the steps of: (a) forming the first LOCOS isolation structure; (b) forming the second LOCOS isolation structure; (c) forming the first trench in the substrate; (d) forming the second trench in the substrate interposed between portions of a second LOCOS isolation structure; (e) forming the isolation material within the first trench; (f) forming the isolation material within the second trench; and wherein at least one of steps (a) and (b), steps (c) and (d), and steps (e) and (f) are performed simultaneously.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.